Optimal MOSFET design for low temperature operation

Abstract

The phenomenal scaling of MOSFET feature size, two orders of magnitude in the past 30 years, has provided the gains in performance and packing density that underlie the GHz microprocessors and 256 MB DRAMs that exist today. Looking forward, the connection between increased performance and smaller devices faces significant challenges. Lowering the operating temperature can help achieve the desired increases in performance as device size scales. Lowering the temperature reduces the off-state leakage of a MOSFET removing constraints on reducing the threshold voltage. In addition, lower temperatures increase the current drive via increased carrier mobility and saturation velocity. Equally as important, the parasitic resistances of the device and of the interconnect decrease as temperature decreases. The approach of this thesis is to use comparisons of optimal designs across channel lengths and across temperatures to accurately assess the performance increases and increased design flexibility that come with lowering the device operating temperature. Using analytical equations, the tradeoff between fully scaled performance and maintaining reasonable off-current levels is clearly shown. As an alternative to allowing off-currents to rise, two possible temperature scaling scenarios, that either meet or exceed fully scaled performance, are explored. Focusing on a nominal channel length of 90 nm (worst-case of 75 nm) operating at 200 K, a detailed analysis of channel doping profile design to achieve the highest on current at the nominal channel length, while meeting the off-current limit for the worst case channel length is performed. Using an inverse modeling approach, a 2-D numerical simulator is first calibrated at various temperatures to measured device data down to 80 nm channel lengths. Coupling the simulator with an optimizer, a range of different halo, retrograde, and uniform doping profiles are examined. Halo doping is found to give the best device performance due to its lower threshold voltage, lower threshold voltage decrease with channel length, and lower body effect. The halo profiles become more abrupt for lower temperature designs. Comparing optimal designs for a 90 nm nominal device across temperature, on-current gains, and thus switching speed gains, of 3.5% for every 10 °C decrease in temperature can be achieved.