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6.823 Computer System Architecture, Spring 2002

dc.contributor.authorAsanovic, Krsteen_US
dc.contributor.authorArvind, V.en_US
dc.contributor.authorDevadas, Srinivasen_US
dc.contributor.authorHoe, James C. (James Chu-Yue)en_US
dc.coverage.temporalSpring 2002en_US
dc.date.issued2002-06
dc.identifier6.823-Spring2002
dc.identifierlocal: 6.823
dc.identifierlocal: IMSCP-MD5-96dcefd5806926cb33055fc1fc7c4490
dc.identifier.urihttp://hdl.handle.net/1721.1/35849
dc.description.abstractEmphasizes the relationship among technology, hardware organization, and programming systems in the evolution of computer architecture. Pipelined, out-of-order, and speculative execution. Superscaler, VLIW, vector, and multithreaded processors. Addressing structures and virtual memory, and exception handling. I/O and memory systems. Parallel computers; message passing and shared memory systems. Memory models, synchronization, and cache coherence protocols. Vector supercomputers. Assumes an undergraduate knowledge of computer systems. From the course home page: Course Description 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.en_US
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dc.languageen-USen_US
dc.rights.uriUsage Restrictions: This site (c) Massachusetts Institute of Technology 2003. Content within individual courses is (c) by the individual authors unless otherwise noted. The Massachusetts Institute of Technology is providing this Work (as defined below) under the terms of this Creative Commons public license ("CCPL" or "license"). The Work is protected by copyright and/or other applicable law. Any use of the work other than as authorized under this license is prohibited. By exercising any of the rights to the Work provided here, You (as defined below) accept and agree to be bound by the terms of this license. The Licensor, the Massachusetts Institute of Technology, grants You the rights contained here in consideration of Your acceptance of such terms and conditions.en_US
dc.subjectcomputer architectureen_US
dc.subjectcomputer system architectureen_US
dc.subjecthardwareen_US
dc.subjecthardware designen_US
dc.subjectsoftwareen_US
dc.subjectsoftware designen_US
dc.subjectinstruction set designen_US
dc.subjectprocessor micro-architectureen_US
dc.subjectpipeliningen_US
dc.subjectcache memoryen_US
dc.subjectvirtual memoryen_US
dc.subjectI/Oen_US
dc.subjectinput/outputen_US
dc.subjectinterruptsen_US
dc.subjectsuperscalar architecturesen_US
dc.subjectVLIW machinesen_US
dc.subjectvector supercomputersen_US
dc.subjectmultithreaded architecturesen_US
dc.subjectsymmetric multiprocessorsen_US
dc.subjectparallel computersen_US
dc.subjectComputer architectureen_US
dc.title6.823 Computer System Architecture, Spring 2002en_US
dc.title.alternativeComputer System Architectureen_US


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