Scalable Packaging and Integration Solutions for Next-Generation Photonic Systems

Abstract

The ever-increasing demand for faster and more efficient computation has propelled the rapid growth of integrated photonics, with commercial products starting to reach global markets in recent years. Nevertheless, integrated photonics still lacks the scale required to meet market demands and falls short of the performance targets necessary for many critical applications. Innovative solutions are imperative if photonics is to drive technological advancement and become a ubiquitous part of next-generation systems, rather than being confined to niche or high-end applications. Among the key bottlenecks is photonics packaging, which refers to the challenge of electrically, optically, and thermally interfacing with a photonic integrated circuit (PIC). Current packaging solutions often impose significant design tradeoffs, contributing to industry fragmentation and high costs. Two-photon lithography (TPL), a high-resolution 3D manufacturing technique, has emerged as a promising enabler of robust and efficient optical interconnects. However, existing research has focused heavily on performance, often relying on additional chip processing steps (e.g., cladding removal) that hinder scalability. Moreover, prior work largely restricts itself to parameterized geometries, such as quadratic curves or spherical sections, that underutilize the true design freedom of TPL. My work addresses both of these limitations. I developed a freeform, facet-attached micro-reflector solution that is fully compatible with standard foundry processes, adaptable to challenging coupling scenarios, and computationally efficient to design. This coupling solution demonstrates all the properties desired in an ideal optical interface: low insertion loss (~0.6 dB), wide bandwidth (>300 nm), foundry compatibility, and geometric universality across PIC platforms. Another major challenge facing the photonics industry is the lack of critical functionalities within current foundry processes due to limited material availability. Significant gains in performance and capability can be realized by integrating new materials on-chip, but doing so while maintaining CMOS-foundry compatibility remains a formidable task. To address this, I helped develop a novel photonics platform enabling substrate-inverted multi-material integration. This platform supports seamless integration of diverse materials while leveraging existing PIC process stacks, including metallization layers, unlocking new classes of high-performance devices. Building on this idea, I further demonstrated how material integration can directly enable new applications. Specifically, I developed a selective and ultra-sensitive environmental lead (Pb²⁺) sensor, based on a crown ether functionalization layer. This device showcases the potential of hybrid material platforms to deliver practical, field-relevant solutions in environmental monitoring and beyond.