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dc.contributor.advisorJonathan Allen.en_US
dc.contributor.authorBamji, Cyrus Sen_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-08-10T18:57:40Z
dc.date.available2005-08-10T18:57:40Z
dc.date.copyright1989en_US
dc.date.issued1990en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/13999
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990.en_US
dc.descriptionIncludes bibliographical references (leaves 193-196).en_US
dc.description.statementofresponsibilityby Cyrus S. Bamji.en_US
dc.format.extent196 leavesen_US
dc.format.extent14621940 bytes
dc.format.extent14621696 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleGraph-based representations and coupled verification of VLSI schematics and layoutsen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc23117187en_US


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