Browsing LCS Technical Memos (1974 - 2003) by Author "Lee, Walter"
Now showing items 1-7 of 7
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How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture
Taylor, Michael Bedford; Lee, Walter; Frank, Matthew; Amarasinghe, Saman; Agarwal, Anant (2000-04)The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures ... -
Maps: a Compiler-Managed Memory System for RAW Machines
Barua, Rajeev; Lee, Walter; Amarasinghe, Saman; Agarwal, Anant (1998-07)Microprocessors of the next decade and beyond will be built using VLSI chips employing billions of transistors. In this generation of microprocessors, achieving a high level of parallelism at a reasonable clock speed will ... -
A Software Framework for Supporting General Purpose Applications on RAW Computation Fabrics
Frank, Matthew; Lee, Walter; Amarasinghe, Saman (2001-07)This paper presents SUDS (Software Un-Do Systems), a data speculation system for Raw processors. SUDS manages specultation in software. Thekey to managing speculation in software is to use the compiler to minimize the ... -
Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Lee, Walter; Barua, R.; Srikrishna, D.; Babb, Jonathan; Sarkar, V.; e.a. (1997-12)Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. ... -
Strength Reduction of Integer Division and Modulo Operations
Amarasinghe, Saman; Lee, Walter; Greenwald, Ben (1999-11)Integer division, modulo, and remainder operations are expressive and useful operations. They are logical candidates to express complex data accesses such as the wrap-around behavior in queues using ring buffers, array ... -
A Theoretical and Practical Approach to Instruction Scheduling on Spatial Architectures
Mirrokni, Vahab S.; Lee, Walter; Karger, David; Amarasinghe, Saman (2002-12)This paper studies the problem of instruction assignment and scheduling on spatial architectures. Spatial architectures are architectures whose resources are organized in clusters, with non-zero communication delays between ... -
UDM: User Direct Messaging for General-Purpose Multiprocessing
Mackenzie, Kenneth; Kubiatowicz, John; Frank, Matthew; Lee, Walter; Victor, Lee; e.a. (1996-03)User Direct Messaging (UDM) allows user-level, processor-to- processor messaging to coexist with general multiprogramming and virtual memory. Direct messaging, where processors launch and receive messages in tens of cycles ...