Now showing items 1-17 of 17

    • Bitwidth Analysis with Application to Silicon Compilation 

      Stephenson, Mark; Babb, Jonathan; Amarasinghe, Saman (1999-11)
      In this paper introduces Bitwise, a compiler that minimizes the bitwidth - the number of bits used to represent each operand - for both integers and pointers in a program. By propagating static information both forward and ...
    • Execution Model Enforcement Via Program Shepherding 

      Kiriansky, Vladimir; Bruening, Derek; Amarasinghe, Saman (2003-05)
      Nearly all security attacks have one thing in common: they coerce the target program into performing actions that it was never intended to perform. In short, they violate the program's execution model. The execution model ...
    • Exploiting Superword Level Parallelism with Multimedia Instruction Sets 

      Larsen, Samuel; Amarasinghe, Saman (1999-11)
      Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general-purpose microprocessors. This added functionality comes primarily in the addition of short SIMD ...
    • How to Build Scalable On-Chip ILP Networks for a Decentralized Architecture 

      Taylor, Michael Bedford; Lee, Walter; Frank, Matthew; Amarasinghe, Saman; Agarwal, Anant (2000-04)
      The era of billion transistors-on-a-chip is creating a completely different set of design constraints, forcing radically new microprocessor archiecture designs. This paper examines a few of the possible microarchitectures ...
    • Maps: a Compiler-Managed Memory System for RAW Machines 

      Barua, Rajeev; Lee, Walter; Amarasinghe, Saman; Agarwal, Anant (1998-07)
      Microprocessors of the next decade and beyond will be built using VLSI chips employing billions of transistors. In this generation of microprocessors, achieving a high level of parallelism at a reasonable clock speed will ...
    • Phased Computation Graphs in the Polyhedral Model 

      Thies, William; Lin, Jasper; Amarasinghe, Saman (2002-08)
      We present a translation scheme that allows a broad class of dataflow graphs to be considered under the optimization framework of the polyhedral model. The input to our analysis is a Phased Computation Graph, which we ...
    • Secure Execution Via Program Shepherding 

      Kiriansky, Vladimir; Bruening, Derek; Amarasinghe, Saman (2002-02)
      We introduce program shepherding, a method for monitoring control flow transfers during program execution to enforce a security policy. Shepherding ensures that malicious code masquerading as data is never executed, thwarting ...
    • Softspec: Software-based Speculative Parallelism 

      Bruering, Derek; Devabhaktuni, Srikrishna; Amarasinghe, Saman (2000-04)
      We present Softspec, a technique for parallelizing sequential applications using only simple software mechanisms, requiring no complex program analysis or hardware support. Softspec parallelizes loops whose memory references ...
    • A Software Framework for Supporting General Purpose Applications on RAW Computation Fabrics 

      Frank, Matthew; Lee, Walter; Amarasinghe, Saman (2001-07)
      This paper presents SUDS (Software Un-Do Systems), a data speculation system for Raw processors. SUDS manages specultation in software. Thekey to managing speculation in software is to use the compiler to minimize the ...
    • Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine 

      Lee, Walter; Barua, R.; Srikrishna, D.; Babb, Jonathan; Sarkar, V.; e.a. (1997-12)
      Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. ...
    • A Stream Compiler for Communication-Exposed Architectures 

      Gordon, Michael; Thies, William; Karczmarek, Michael; Wong, Jeremy; Hoffmann, Henry; e.a. (2002-03)
      With the increasing miniturization of transistors, wire delays are becoming a dominant factor in microprocessor performance. To address this issue, a number of emerging architectures contain replicated processing units ...
    • StreamIT: A Complier for Streaming Applications 

      Thies, William F.; Karczmarek, Michael; Gordon, Michael; Maze, David; Wong, Jeremy; e.a. (2002-02)
      Streaming programs represent an increasingly important and widespread class of applications that holds unprecedented opportunitie sfor high-impact compiler technology. Unlike sequential programs with obscured dependence ...
    • StreaMIT: A Language for Streaming Applications 

      Thies, William F.; Karczmarek, Michael; Amarasinghe, Saman (2001-08)
      We characterize high-performance streaming applications as a new and distinct domain of programs that is becoming increasingly important. The StreaMIT language provides novel high-level representations to improve programmer ...
    • Strength Reduction of Integer Division and Modulo Operations 

      Amarasinghe, Saman; Lee, Walter; Greenwald, Ben (1999-11)
      Integer division, modulo, and remainder operations are expressive and useful operations. They are logical candidates to express complex data accesses such as the wrap-around behavior in queues using ring buffers, array ...
    • Techniques for Increasing and Detecting Memory Alignment 

      Larsen, Samuel; Witchel, Emmett; Amarasinghe, Saman (2001-11)
      Memory alignment is an important property in memory system performance. Extraction of alignment information at compile-time enables the possibility for new classes of program optimization. In this paper, we present methods ...
    • A Theoretical and Practical Approach to Instruction Scheduling on Spatial Architectures 

      Mirrokni, Vahab S.; Lee, Walter; Karger, David; Amarasinghe, Saman (2002-12)
      This paper studies the problem of instruction assignment and scheduling on spatial architectures. Spatial architectures are architectures whose resources are organized in clusters, with non-zero communication delays between ...
    • A Unified Framework for Schedule and Storage Optimization 

      Thies, William F.; Viven, Frederic; Sheldon, Jeffery W.; Amarasinghe, Saman (2000-11)
      We present a unified mathematical framework for analyzing the tradeoffs between parallelism and storage allocation within a parallelizing compiler. Using this framework, we show how to find the best storage mapping for a ...