A Data Flow Architecture with Improved Asymptotic Performance
| dc.contributor.author | Thomas, Robert E. | en_US |
| dc.date.accessioned | 2023-03-29T15:05:39Z | |
| dc.date.available | 2023-03-29T15:05:39Z | |
| dc.date.issued | 1981-04 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149543 | |
| dc.description.abstract | Large scale integration presents a unique opportunity to design a computer compromising large numbers of small, inexpensive processors. This paper presents a design for such a machine based on the asynchronous and functional semantics of data flow. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-265 | |
| dc.title | A Data Flow Architecture with Improved Asymptotic Performance | en_US |
| dc.identifier.oclc | 9479518 |
