Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed -Memory Multiprocess
Author(s)
Barua, Rajeev; Kranz, David; Agarwal, Anant
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Harnessing the full performance potential of cache-coherent distributed shared memory multiprocessors without inordinate user effort requires a compilation technology that can automatically manage multiple levels of memory hierarchy. This paper describes a working compiler for such machines that automatically partitions loops and data arrays to optimize locality of access.
Date issued
1995-01Series/Report no.
MIT-LCS-TM-522