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dc.contributor.authorLeighton, Frank Thomsonen_US
dc.date.accessioned2023-03-29T14:21:49Z
dc.date.available2023-03-29T14:21:49Z
dc.date.issued1982-08
dc.identifier.urihttps://hdl.handle.net/1721.1/149037
dc.description.abstractIn this paper, we use crossing number and wire area arguments to find lower bounds on the layout area and maximum edge length of a variety of new and computationally useful networks. In particular, we describe 1) an N-node planar graph which has layout area ⊖ (NlogN) and maximum edge length ⊖(N^1/2/log^1/2N), 2) an N-node graph with an O(x^1/2)-separator which has layout area ⊖ (Nlog^2N) and maximum edge length ⊖ (N^1/2logN/loglogN), and 3) an N-node graph with an O(x^1-1/r)-separator which has maximum edge length ⊖(N1-1/4) for an r≥3.en_US
dc.relation.ispartofseriesMIT-LCS-TM-227
dc.titleNew Lower Bound Techniques For VLSIen_US
dc.identifier.oclc9824908


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